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| M27C256B 256 Kbit (32Kb x 8) UV EPROM and OTP EPROM s 5V 10% SUPPLY VOLTAGE in READ OPERATION ACCESS TIME: 45ns LOW POWER CONSUMPTION: - Active Current 30mA at 5MHz - Standby Current 100A 28 s s 28 s s s PROGRAMMING VOLTAGE: 12.75V 0.25V PROGRAMMING TIME: 100s/word ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code: 8Dh 1 1 FDIP28W (F) PDIP28 (B) DESCRIPTION The M27C256B is a 256 Kbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems and is organized as 32,768 by 8 bits. The FDIP28W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C256B is offered in PDIP28, PLCC32 and TSOP28 (8 x 13.4 mm) packages. PLCC32 (C) TSOP28 (N) 8 x 13.4 mm Figure 1. Logic Diagram VCC VPP 15 A0-A14 8 Q0-Q7 E G M27C256B VSS AI00755B August 2002 1/16 M27C256B Figure 2A. DIP Connections Figure 2B. LCC Connections AI00756 VSS DU Q3 Q4 Q5 AI00757 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS 28 1 27 2 26 3 25 4 24 5 23 6 22 7 M27C256B 21 8 20 9 19 10 18 11 17 12 13 16 14 15 VCC A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3 A7 A12 VPP DU VCC A14 A13 1 32 A6 A5 A4 A3 A2 A1 A0 NC Q0 A8 A9 A11 NC G A10 E Q7 Q6 9 M27C256B 25 17 Q1 Q2 A0-A14 Q0-Q7 Figure 2C. TSOP Connections Table 1. Signal Names Address Inputs Data Outputs Chip Enable Output Enable Program Supply Supply Voltage Ground Not Connected Internally Don't Use G A11 A9 A8 A13 A14 VCC VPP A12 A7 A6 A5 A4 A3 22 21 28 1 M27C256B 15 14 7 8 AI00614B A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 E G VPP VCC VSS NC DU 2/16 M27C256B Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (2) VCC VA9 (2) VPP Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage (except A9) Supply Voltage A9 Voltage Program Supply Voltage Value -40 to 125 -50 to 125 -65 to 150 -2 to 7 -2 to 7 -2 to 13.5 -2 to 14 Unit C C C V V V V Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is -0.5V with possible undershoot to -2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes Mode Read Output Disable Program Verify Program Inhibit Standby Electronic Signature Note: X = VIH or VIL, VID = 12V 0.5V. E VIL VIL VIL Pulse VIH VIH VIH VIL G VIL VIH VIH VIL VIH X VIL A9 X X X X X X VID VPP VCC VCC VPP VPP VPP VCC VCC Q7-Q0 Data Out Hi-Z Data In Data Out Hi-Z Hi-Z Codes Table 4. Electronic Signature Identifier Manufacturer's Code Device Code A0 VIL VIH Q7 0 1 Q6 0 0 Q5 1 0 Q4 0 0 Q3 0 1 Q2 0 1 Q1 0 0 Q0 0 1 Hex Data 20h 8Dh 3/16 M27C256B Table 5. AC Measurement Conditions High Speed Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V Standard 20ns 0.4V to 2.4V 0.8V and 2V Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit 1.3V High Speed 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V AI01822 1N914 3.3k Standard 2.4V OUT CL 0.4V CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance AI01823B Table 6. Capacitance (1) (TA = 25 C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. DEVICE OPERATION The operating modes of the M27C256B are listed in the Operating Modes. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature. Read Mode The M27C256B has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the ad- dresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27C256B has a standby mode which reduces the supply current from 30mA to 100A. The M27C256B is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. 4/16 M27C256B Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70C, -40 to 85C, -40 to 105C or -40 to 125C; VCC = 5V 5% or 5V 10%; VPP = VCC) Symbol ILI ILO ICC ICC1 ICC2 IPP VIL VIH (2) VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS IOL = 2.1mA IOH = -1mA IOH = -100A 3.6 VCC - 0.7V Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIL, IOUT = 0mA, f = 5MHz E = VIH E > VCC - 0.2V VPP = VCC -0.3 2 Min Max 10 10 30 1 100 100 0.8 VCC + 1 0.4 Unit A A mA mA A A V V V V V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V. Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70C, -40 to 85C, -40 to 105C or -40 to 125C; VCC = 5V 5% or 5V 10%; VPP = VCC) M27C256B Symbol Alt Parameter Test Condition -45 (3) Min tAVQV tELQV tGLQV tEHQZ (2) tGHQZ (2) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 Max 45 45 25 25 25 0 0 0 -60 Min Max 60 60 30 30 30 0 0 0 -70 Min Max 70 70 35 30 30 0 0 0 -80 Min Max 80 80 40 30 30 ns ns ns ns ns ns Unit Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 3. Speed obtained with High Speed AC measurement conditions. Two Line Output Control Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device. 5/16 M27C256B Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70C, -40 to 85C, -40 to 105C or -40 to 125C; VCC = 5V 5% or 5V 10%; VPP = VCC) M27C256B Symbol Alt Parameter Test Condition -90 Min tAVQV tELQV tGLQV tEHQZ (2) tGHQZ (2) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 Max 90 90 40 30 30 0 0 0 -10 Min Max 100 100 50 30 30 0 0 0 -12 Min Max 120 120 60 40 40 0 0 0 -15/-20/-25 Unit Min Max 150 150 65 50 50 ns ns ns ns ns ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. Figure 5. Read Mode AC Waveforms A0-A14 VALID tAVQV tAXQX VALID E tGLQV G tELQV Q0-Q7 tGHQZ Hi-Z tEHQZ AI00758B System Considerations The power switching characteristics of Advance CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of this transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line 6/16 output control and by properly selected decoupling capacitors. It is recommended that a 0.1F ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7F bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. M27C256B Table 9. Programming Mode DC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V) Symbol ILI ICC IPP VIL VIH VOL VOH VID Parameter Input Leakage Current Supply Current Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL A9 Voltage IOL = 2.1mA IOH = -1mA 3.6 11.5 12.5 E = VIL -0.3 2 Test Condition VIL VIN VIH Min Max 10 50 50 0.8 VCC + 0.5 0.4 Unit A mA mA V V V V V Note: VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Table 10. Programming Mode AC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V Symbol tAVEL tQVEL tVPHEL tVCHEL tELEH tEHQX tQXGL tGLQV tGHQZ tGHAX Alt tAS tDS tVPS tVCS tPW tDH tOES tOE tDFP tAH Parameter Address Valid to Chip Enable Low Input Valid to Chip Enable Low VPP High to Chip Enable Low VCC High to Chip Enable Low Chip Enable Program Pulse Width Chip Enable High to Input Transition Input Transition to Output Enable Low Output Enable Low to Output Valid Output Enable High to Output Hi-Z Output Enable High to Address Transition 0 0 Test Condition Min 2 2 2 2 95 2 2 100 130 105 Max Unit s s s s s s s ns ns ns Note: VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Programming When delivered (and after each erasure for UV EPROM), all bits of the M27C256B are in the "1" state. Data is introduced by selectively programming "0"s into the desired bit locations. Although only "0"s will be programmed, both "1"s and "0"s can be present in the data word. The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The M27C256B is in the programming mode when VPP input is at 12.75V, G is at VIH and E is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V 0.25 V. 7/16 M27C256B Figure 6. Programming and Verify Modes AC Waveforms A0-A14 tAVEL Q0-Q7 DATA IN tQVEL VPP tVPHEL VCC tVCHEL E tELEH G VALID DATA OUT tEHQX tGLQV tGHQZ tGHAX tQXGL PROGRAM VERIFY AI00759 Figure 7. Programming Flowchart VCC = 6.25V, VPP = 12.75V n=0 E = 100s Pulse NO ++n = 25 YES NO VERIFY YES Last Addr NO ++ Addr FAIL YES CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V AI00760B PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows to program the whole array with a guaranteed margin, in a typical time of 3.5 seconds. Programming with PRESTO II involves the application of a sequence of 100s program pulses to each byte until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides necessary margin to each programmed cell. Program Inhibit Programming of multiple M27C256Bs in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27C256B may be common. A TTL low level pulse applied to a M27C256B's E input, with VPP at 12.75V, will program that M27C256B. A high level E input inhibits the other M27C256Bs from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with G at VIL, E at VIH, VPP at 12.75V and VCC at 6.25V. 8/16 M27C256B Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25C 5C ambient temperature range that is required when programming the M27C256B. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27C256B, with VCC = VPP = 5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from V IL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the STMicroelectronics M27C256B, these two identifier bytes are given in Table 4 and can be read-out on outputs Q7 to Q0. ERASURE OPERATION (applies for UV EPROM) The erasure characteristics of the M27C256B is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 A. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 A range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27C256B in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27C256B is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27C256B window to prevent unintentional erasure. The recommended erasure procedure for the M27C256B is exposure to short wave ultraviolet light which has wavelength 2537A. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 W/cm2 power rating. The M27C256B should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure. 9/16 M27C256B Table 11. Ordering Information Scheme Example: Device Type M27 Supply Voltage C = 5V Device Function 256B = 256 Kbit (32Kb x 8) Speed -45 (1) = 45 ns -60 = 60 ns -70 = 70 ns -80 = 80 ns -90 = 90 ns -10 = 100 ns -12 = 120 ns -15 = 150 ns -20 = 200 ns -25 = 250 ns VCC Tolerance blank = 10% X = 5% Package F = FDIP28W B = PDIP28 C = PLCC32 N = TSOP28: 8 x 13.4 mm Temperature Range 1 = 0 to 70 C 3 = -40 to 125 C 6 = -40 to 85 C Options X = Additional Burn-in TR = Tape & Reel Packing M27C256B -70 X C 1 TR Note: 1. High Speed, see AC Characteristics section for further information. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 10/16 M27C256B Table 12. Revision History Date July 1998 20-Sep-2000 29-Nov-2000 02-Apr-2001 29-Aug-2002 Version 1.0 1.1 1.2 1.3 1.4 First Issue AN620 Reference removed PLCC codification changed (Table 11) FDIP28W mechanical dimensions changed (Table 13) Package mechanical data clarified for PDIP28 (Table 14), PLCC32 (Table 15, Figure 10) and TSOP28 (Table 16, Figure 11) Revision Details 11/16 M27C256B Table 13. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data Symbol A A1 A2 A3 B B1 C D D2 E E1 e eA eB L S N 7.11 2.54 14.99 33.02 15.24 1.45 0.51 3.91 3.89 0.41 - 0.23 36.50 - - 13.06 - - 16.18 3.18 1.52 - 4 28 millimeters Typ Min Max 5.72 1.40 4.57 4.50 0.56 - 0.30 37.34 - - 13.36 - - 18.03 4.10 2.49 - 11 0.280 0.100 0.590 1.300 0.600 0.057 0.020 0.154 0.153 0.016 - 0.009 1.437 - - 0.514 - - 0.637 0.125 0.060 - 4 28 Typ inches Min Max 0.225 0.055 0.180 0.177 0.022 - 0.012 1.470 - - 0.526 - - 0.710 0.161 0.098 - 11 Figure 8. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline A2 A3 A1 B1 B D2 D S N 1 A L eA eB C e E1 E FDIPW-a Drawing is not to scale. 12/16 M27C256B Table 14. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Mechanical Data millimeters Symbol Typ A A1 A2 B B1 C D D2 E E1 e1 eA eB L S N 3.300 1.78 0 28 2.08 10 36.830 33.020 15.240 13.720 2.540 15.000 12.700 - 14.800 15.200 14.480 - 15.200 16.680 0.1299 0.070 0 28 0.082 10 4.445 0.630 3.810 0.450 1.270 0.230 36.580 - 0.310 37.080 - 1.4500 1.3000 0.6000 0.5402 0.1000 0.5906 0.5000 - 0.5827 0.5984 0.5701 - 0.5984 0.6567 3.050 4.570 Min Max Typ 0.1750 0.0248 0.1500 0.0177 0.0500 0.0091 1.4402 - 0.0122 1.4598 - 0.1201 0.1799 Min Max inches Figure 9. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline A2 A1 B1 B D2 D S N A L eA eB C e1 E1 1 E PDIP Drawing is not to scale. 13/16 M27C256B Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data Symbol A A1 A2 B B1 CP D D1 D2 D3 E E1 E2 E3 e F R N 0.89 10.16 1.27 7.62 12.32 11.35 4.78 - 14.86 13.89 6.05 - - 0.00 - 32 millimeters Typ Min 3.18 1.53 0.38 0.33 0.66 Max 3.56 2.41 - 0.53 0.81 0.10 12.57 11.51 5.66 - 15.11 14.05 6.93 - - 0.13 - 0.035 0.400 0.050 0.300 0.485 0.447 0.188 - 0.585 0.547 0.238 - - 0.000 - 32 Typ inches Min 0.125 0.060 0.015 0.013 0.026 Max 0.140 0.095 - 0.021 0.032 0.004 0.495 0.453 0.223 - 0.595 0.553 0.273 - - 0.005 - Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline D D1 1N A1 A2 B1 E2 E3 E1 E e F 0.51 (.020) 1.14 (.045) D3 R CP A E2 B D2 D2 PLCC-A Drawing is not to scale. 14/16 M27C256B Table 16. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm, Package Mechanical Data millimeters Symbol A A1 A2 B C CP D D1 e E L N 0.550 13.200 11.700 - 7.900 0.500 0 28 0.950 0.170 0.100 Typ Min Max 1.250 0.200 1.150 0.270 0.210 0.100 13.600 11.900 - 8.100 0.700 5 0.0217 0.5197 0.4606 - 0.3110 0.0197 0 28 0.0374 0.0067 0.0039 Typ inches Min Max 0.0492 0.0079 0.0453 0.0106 0.0083 0.0039 0.5354 0.4685 - 0.3189 0.0276 5 Figure 11. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm, Package Outline A2 1 N e E B N/2 D1 D A CP DIE C TSOP-a A1 L Drawing is not to scale 15/16 M27C256B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 16/16 |
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